(1) Field of the Invention
The invention relates generally to electronic circuits for protecting a battery, and more particularly, to a circuit for controlling the charging, discharging, and protection of a rechargeable battery.
2. Description of the Prior Art
Rechargeable batteries are used in a variety of applications, especially for portable electronic devices. In particular, rechargeable batteries are substantial components of portable phones, personal data assistants and digital cameras. Several types of batteries are used in the art, most notably those comprising lithium ion (Li+). For optimum battery life and performance, rechargeable batteries must be protected from excessive charging voltages during recharging and from over discharging while supplying the appliance. The control circuits and switches used for these tasks have to sustain the occuring voltages and currents and also have to operate with an acceptable degree of efficiency. The reliable and cost-effective manufacturing of such circuits, at its best containing all the necessary components within one single integrated circuit is a desirable demand.
Realizations of the prior art for such circuits are often implemented as specifically assembled semiconductor circuit systems, consisting of integrated control circuits combined with separate external switching devices considering the specific voltage and current requirements. FIG. 1 prior art is a commonly used configuration and shown here as an exemplary prior art and showcase battery protection circuit mainly for explanatory purposes. A rechargeable battery 10 is configured such that it can source energy to a load 20 or can be recharged by a charger source 25, both connected to the terminals LOAD/CHARGE 80 and GND 60. Two MOSFET switches N1 31 and N2 32 are used to control the flow of current into (then charging) and out of (then discharging) the battery. The control circuit 50 controls the ON and OFF state of the switches 31 and 32. Typically, the switches comprise discrete devices. Each switch 31 and 32 contains a parasitic bulk-to-drain diode D1 41 and D2 42. By coupling each switch in an opposite manner, each of the parasitic diodes 41 and 42 conducts current in a different direction.
During normal charging or discharging of the battery 10, both of the switches are ON. However, if the control circuit 50 detects an over charging voltage from VBATT 70 to GND 60, then the control circuit turns OFF the switch N1. Since the parasitic diode D1 41 also blocks current flow into the battery, the battery stops charging. In the case of an over discharging condition, the control circuit 50 would detect a too low battery voltage from VBATT 70 to GND 60. The other switch N2 32 would be turned OFF. In this case, the parasitic diode D2 42 blocks current flow out of the battery 10. As typical values for the voltages may be given: 2 . . . 4 V for the rechargeable battery and for the load and 12 V for the charger voltage, with currents up to 500 mA.
Referring now to FIG. 2 prior art, a second realization of such protective circuits is illustrated. In this case, two NMOS FET switches N1 (item 201) and N2 (item 202) are used. N1 and N2 are cascaded to provide a combined switch having a larger operating voltage range than is available with a single switch. This is a configuration as developed for the related patent “Power Switch for Battery Protection” and shown here operating in the normal charging or discharging modes (*) see Table 1). By nature, the battery-charging source (item 450) is capable of generating a larger voltage than the battery (item 100). When an over charge condition is detected, and a single switch solution is turned OFF, the voltage difference between the charger (item 450) and the battery (item 100) must be sustained across that switch. The voltage range of the switches is limited by the drain-to-bulk reverse breakdown as given be the manufacturing process. This breakdown voltage may be about 7 Volts for a single FET, for example. This means that the charger design must be limited to not generate a voltage greater than the battery voltage plus the breakdown voltages of the FETs. The use of the cascaded NMOS FET devices N1 (item 201) and N2 (item 202) increases the operating range of the combined switch in such a way, that a voltage difference of, for example, about 14 Volts can be sustained in the OFF state. The first FET switch N1 has gate, source, drain, and bulk. The drain is coupled to the negative battery terminal, GND (item 500). The bulk is coupled switchable between the negative battery terminal GND and a middle node MID (item 550) between the cascaded FET devices N1 (item 201) and N2 (item 202). The second FET switch N2 (item 202) also has gate, source, drain, and bulk. The drain is coupled to the first FET switch N1 source at the mid node MID (item 550). The source is coupled to the load terminal node GNDOUT (item 590). The bulk of N2 (item 202) is coupled switchable between MID (item 550) and the load terminal GNDOUT (item 590). The control circuit drives the gates of N1 (item 601) and N2 (item 602) and the bulk switches SW1 (item 203), SW2 (item 205), SW3 (item 204), and SW4 (item 206).
The operating table for this circuit using cascaded NMOS FET switches is shown as Table 1 below.
TABLE 1Operating modes for Cascaded NMOS Circuit.ModeN1BULK N1N2BULK N2Charging *)ONSW2 ONONSW4 ONOver ChargingOFFSW2 ONOFFSW4 ONCharging in OverONSW2 ONMOSSW4 ONDischarged StateDIODEDischarging *)ONSW1 ONONSW3 ONOver DischargingONSW1 ONOFFSW3 ONDischarging inONSW1 ONMOSSW3 ONOver ChargedDIODEState
When the circuit is in the charging or discharging mode, both of the transistors N1 and N2 are ON. The bulk of N1 (item 201) is coupled to the MID node (item 550) by turning ON SW2 (item 205). The bulk of N2 (item 202) is coupled to the load terminal GNDOUT (item 590) by turning ON SW4 (item 205). If an over charging condition is detected, the control circuit turns OFF both switches N1 and N2 to interrupt current flow. The configuration of the bulks presents a series of reversed biased p-n junctions between the negative battery terminal GND (item 500) and the load terminal GNDOUT (item 590) to thereby block-charging current. The use of two NMOS devices allows the voltage difference between GND (item 500) and GNDOUT (item 590) to drop across two bulk-to-drain diodes and thereby increases the operating range when compared to a single-transistor approach. If an over discharge event is detected, the control circuit turns OFF N2 (item 202). In this case, however the bulk of N1 (item 201) is coupled to GND (item 500) by SW1 (item 203) and the bulk of N2 (item 202) is coupled to MID (item 550) by SW3 (item 204). This creates a series of reverse biased p-n diodes from the GNDOUT (item 590) to GND (item 500). Discharging current flow is thereby stopped by the channel of N2 (item 202) and the reverse-biased diodes. In the charging an over discharged battery case and in the discharging the over charged battery case, the cascaded circuit works as shown in Table 1. Note that the first transistor N1 (item 201) is held ON for both cases. However, the second transistor N2 (item 202) is biased to the MOS diode case to protect the battery. Additionally a resistive voltage divider Z1 (item 220) and Z2 (item 230) is added for the clamping of the MID potential via switch SW5 (item 210) in the cases, where both FETs N1 (item 201) and N2 (item 202) are OFF.
Such prior art circuits have several drawbacks. Li-Ion batteries for example, need an electronic protection to guarantee, that the battery cannot be overcharged or deep-discharged. Actual protection circuits contain a control circuit and external MOSFETs. In case of malfunction high positive or negative voltages will occur across the MOSFETs. These malfunctions also include the erroneous connection of the charger with wrong polarity, thus leading to an operation of the charger in reverse condition. Discrete MOSFETs are able to withstand voltages up to 30 V positive and negative, but with the drawback of a multiple component solution. The main disadvantages however with the use of discrete components are the increase of the manufacturing cost (higher assembly cost) and also its larger physical size (greater space requirements). A completely integrated version (MOSFETs integrated into the control circuit) is normally limited in its voltage range across the MOSFETs to +12 V (forward direction) and to −2 V (reverse direction) due to the breakthrough voltages of the MOS—devices. It is therefore a challenge for the designer of such circuits to achieve a high quality solution, especially with regard to the faulty case when trying to charge under reversed voltage conditions, i.e. voltages with wrong polarity, where the very low breakdown voltages of the MOS-devices in reverse direction are the limiting specifications.
There are several efforts and labors with various patents referring to such approaches.
U.S. Pat. No. 5,877,534 (to Williams, et al.) describes a method of forming an electrostatic discharge protection device for integrated circuits, where an electrostatic discharge (ESD) device includes a pair of depletion mode MOSFETs connected drain-to-drain in a series path between an input terminal and an output terminal, the gate of each MOSFET being connected to its source. A first diode having a relatively high breakdown voltage is connected between ground and the common drain terminal of the MOSFETs, and a second diode having a relatively low breakdown voltage is connected between ground and the output terminal of the device. The second diode breaks down during a relatively low, long-lived voltage spike (in an automobile, sometimes referred to as a “load dump”), while the second MOSFET saturates, limiting the size of the current through the second diode. The first diode breaks down during a large voltage spike of short duration, such as occurs from an ESD.
U.S. Pat. No. 5,939,908 (to Moore, et al.) discloses a dual FET driver circuit for supplying an electric current to a device having a pair of power FET's connected in series between the device and a power supply.
U.S. Pat. No. 6,154,081 (to Pakkala, et al.) shows a load circuit having extended reverse voltage protection, where an improved reverse voltage protection circuit that protects sensitive electronic devices from damage due to both reversed battery connections and source voltage interruptions. An N-channel protection FET is inversely connected between the negative terminal of the protected device and ground, and the conduction of the protection FET is extended during a reverse transient protection period following interruption of the source voltage. A capacitor connected across the gate-to-source circuit of the protection FET is charged from the source voltage through a low impedance charging circuit including a diode to prevent the capacitor from discharging, and is discharged during an interruption of the source voltage through a high impedance discharging circuit connected in parallel with the charging circuit.